Are you an experienced DFT Engineer looking for your next challenge?

Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Design for Test.

With design centres across the UK, Spain, Hyderabad, and Morocco, we offer the flexibility to base this role in any of our global locations. If you’re interested in exploring future opportunities with us, please click the link below to apply and register your interest.

Purpose of Role

To lead and own chip-level Design for Test execution, driving DFT delivery from architecture definition through pattern generation and silicon bring-up. This role ensures high-quality DFT implementation, effective debug and timing closure across test modes, and provides technical leadership within the team, while acting as a key stakeholder interface to ensure predictable and successful delivery.

Responsibilities

Lead DFT strategy definition, implementation of DFT structures, and verification to ensure chip-level testability and project success.
Serve as an expert in DFT, providing industry-leading technical guidance in specialized areas.
Solve highly complex problems and provide innovative solutions to technical challenges.
Define, plan, and lead large, technically complex projects, ensuring alignment with program goals.
Apply judgment in interpreting results, conducting quantitative analysis, and driving data-informed decisions.
Maintain and promote high-quality outputs across the team, ensuring best practices and consistency.
Collaborate effectively with team members and engineering management, fostering a productive and engaged team environment.
Mentor junior engineers and provide leadership across multi-disciplinary project teams.
Contribute to technical thought leadership through white papers, internal/external presentations, and participation in sales support activities, such as Statements of Work.
Listen to customer feedback, identify opportunities, and work with the Business Team to translate technical insights into business growth.

Qualifications

A degree/masters or PhD in a relevant subject

Essential

Typically 10+ years of experience in Design for Test (DFT) engineering.
Expertise with DFT tools from Siemens or Synopsys, including IJTAG, scan compression, MBIST, SSN, boundary scan, and repair implementation.
Strong experience in ATPG and test coverage improvements, pattern simulation (Zdel/SDF), and diagnosing ATE failures and silicon bring-up.
Solid understanding of DFT principles and architecture, with proven experience designing complex chip-level DFT solutions.
Recognized as a problem solver with the ability to lead or contribute effectively within a DFT team.
Demonstrated capability to lead DFT design projects as an expert or provide industry-leading expertise in specific DFT areas.
Strong project management skills, with the ability to evaluate issues, define solutions, and drive project delivery.

Attributes

Team Leader
Active listening skills
Team organisation and ability to set and change priorities quickly
Ability to motivate a team to work under pressure
Organisation and problem-solving skills
Excellent attention to details
Self-motivated
Conflict resolution
Ability to quantify risks and estimate engineering effort
Able to think outside of the box