Are you an experienced Physical Design Engineer looking for your next challenge?

Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Physical Design.

With design centres across the UK, Spain, Hyderabad, and Morocco, we offer the flexibility to base this role in any of our global locations. If you’re interested in exploring future opportunities with us, please click the link below to apply and register your interest.

Purpose of role

Full Chip Physical Design (PD) Expert is responsible for handling the entire physical implementation process of a complex System-on-Chip (SoC) or ASIC, from initial design handoff (RTL or netlist) to final sign-off for manufacturing (GDSII). This role demands deep expertise across all aspects of the physical design flow and the ability to drive technical decisions at the chip level.

Responsibilities

Display customer intimacy by demonstrating clear and customer focused communication, issue resolution & delivery to beyond expectation and developing this approach with the team.
Taking ownership and responsibility of the fullchip activity assigned and deliver on day-to-day tasks.
Actively participate in social engagements and create a culture of recognition to reward success and enhance collaboration.
Taking ownership of mentoring / coaching PD team working on blocks and training them on fullchip PnR and signoff activities.
Encouraging a culture of appropriate delegating and knowledge sharing.
Supporting the hiring to headcount to address the current and future skills gaps and capability within the team by participating actively in the interviews.
Coordinating and communicating with cross functional teams in defining Physical Design strategies/plans.
Responsible for overseeing and coaching Physical Design Engineering Managers in developing their direct reports.
Keeping up to date with relevant engineering advances in the field and ensure that Aion Silicon is kept at the forefront of the state-of-the-art technologies, methodologies and design processes as used in the industry.
Coordinating representation of Aion Silicon at universities, conferences and trade shows, and presenting technical papers

Essential

Soft skills

Experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
Strong cross-functional communication and leadership skills to drive chip-level closure across RTL, STA, DFT, and packaging teams.
Vast experience in laying out multiple instantiated high performance core designs.
Excellent customer management skills.
Proven track record of defining and conducting Top-level training for the junior team members of PD team building organically the team capability.
Proven problem-solving ability under pressure with focus on quality, ownership, and timely delivery.
Mentor and guide block-level PD engineers on methodology and flow best practices.
Review and approve block-level physical design deliverables before integration.
Lead debug sessions and technical discussions for closure issues.
Able to build trust through open and transparent communication
Reliable and dedicated to deliver on promises and commitments
Able to be Risk and Change alert .
Ability to work under pressure with solid organisational and creative problem-solving skills
Positive mindset, demonstrates Aion SIlicon values and embraces and promotes Aions culture.
Self-organisation and ability to respond to changing priorities quickly with excellent time management skills .

Technical skills

10+ years of physical design experience with proven hands-on expertise in delivering three or more Full-Chip Floorplanning & Integration

Ability to create floorplan from the chip specification document.
Chip-level floorplan creation (macro placement, IO ring, block alignment).
Hierarchical and flat design integration.
Block pin placement, channel planning, and aspect ratio optimization.

Pad and IO Integration

Integrate pad cells, ESD structures, and IO rings into the top-level layout.
Ensure signal and power bumps align correctly with pad locations and IO blocks.

Power Planning & Distribution

Power grid (PG) design and planning.

Multi-voltage domain and power gating implementation.

IR drop and electromigration (EM) analysis and optimization.

Bump Planning

Define bump pitch, pattern (array, staggered, peripheral), and power/signal distribution.

Work with package and power integrity teams to align bump locations with package ball-out and PDN requirements.

Clock Tree Synthesis (CTS)

Design and optimization of multi-level and multi-domain clock trees.

Experience in different multipoint CTS techniques ( for ex: fish bone, H-Tree) for better Skew, latency, and jitter optimization.

Low-power clock techniques (clock gating, mesh trees).

Placement & Routing

Standard cell placement optimization for timing and congestion.

Full-chip and top-level routing (global and detailed).

Crosstalk, antenna, and signal integrity issue mitigation.

Timing Closure:

Owns and manages full-chip timing budgeting across hierarchical blocks — defining, allocating, and validating timing constraints to ensure consistent and convergent timing closure at SoC level.

Static Timing Analysis (STA) for setup/hold closure.

Timing ECOs (cell sizing, buffering, re-routing).

Interface timing management between multiple design blocks.

Tapeout data preparation and documentation.

Physical Verification & Signoff

DRC, LVS, and ERC checks.

Parasitic extraction (RCX) and correlation with STA.

Signoff for IR/EM, noise, and reliability.

Tapeout & Foundry Handoff

GDSII/OASIS generation and validation.

Foundry rule compliance (DRC/LVS deck handling).

Tapeout data preparation and documentation.

EDA tool knowledge essential with either Synopsys (e.g., design compiler, ICC2,Fusion Compiler, ICV, Primetime ,StarRC) and / or Cadence (Genus, Innovus, Tempus, Voltus etc) flows and Mentor Calibre flows

Attributes

Able to build trust through open and transparent communication.

Reliable and dedicated to deliver on promises and commitments.
Ability to work under pressure with solid organisational and creative problem-solving skills.
Positive mindset, demonstrates Aion’s behaviours and embraces and promotes Sondrel culture
Self-organisation and ability to respond to changing priorities quickly with excellent time management skills.
Team player with the ability to guide and mentor more junior team members.
Self-motivated and able to work under own initiative with excellent attention to detail.
Passionate and committed to delivering a high standard of work.
Resilient and always finds a way to succeed.