Job details

Are you an experienced Verification Engineer looking for your next challenge?

Aion Silicon is actively building a pipeline of talented engineers for future opportunities, and we’d love to hear from skilled professionals who are passionate about Verification Engineer.

With design centers across the UK, Spain, Hyderabad, and Morocco, we offer the flexibility to base this role in any of our global locations. If you’re interested in exploring future opportunities with us, please click the link below to apply and register your interest.

Purpose of role

This role leads DV activities across customer projects, serving as the principal technical planner and contributor for SoC, ASIC, and IP verification. Working closely with program management and senior DV leads to execute the full verification lifecycle for customer devices. The role requires direct collaboration with customers, IP vendors, designers, and architects to define efficient, innovative verification strategies that ensure high-quality outcomes. The successful candidate will own and oversee DV activities across multi-site engineering teams, ensuring clear communication, timely issue resolution, and sound technical decision-making to keep projects aligned with schedule, budget, and quality targets.

Responsibilities

· Excellent leadership skills, providing advice and guidance to junior members

· Gather creative and talented technical staff and form a team for achievement of targets

· Provide technical and practical support to engineering team members as required. Provide training and documentation on methodologies and best practice.

· Keep up to date with relevant engineering advances in the field and ensure that Aion Silicon is kept at the forefront of the state-of-the-art technologies, methodologies and certification processes as used in the industry

· Work with broader engineering teams and engineering management to define new or improved methodologies and ways of working. Effectively delegate tasks relating to technical verification and flow development.

· Work with programme management team to identify risks and opportunities, estimate engineering effort and update on progress against project plans.

· Definition of verification strategy, planning and execution and new verification methodology and clear documentation thereof.

· Trialling and deployment of industry-leading EDA tools for verification quality, efficiency, execution and metric analysis.

· Track development activities and administer milestones deliverables.

· Collate engineering data and provide regular feedback to customers and programme management about plans, risks, issues, progress etc.

· Ownership of design blocks and technical leadership of all verification aspects from verification strategy, execution, metrics through to RTL quality for physical design team. Ongoing technical support through to productization.

· Represent Aion Silicon at universities, conferences and meetings and present technical papers

Qualifications

A degree/masters or PhD in a relevant subject

Typically, 10+ years’ experience
Serves as a subject matter expert within a technical discipline with latitude for decision making

Metric driven verification, verification planning, functional coverage, code coverage
SystemVerilog, UVM, ABV
Unit level and top-level verification, testbench architecture design
Experience verifying High-Performance Compute (HPC) architectures, including:
- CPU verification
- Interconnect verification
- Verifying Inter-die or Chip-Chip high-speed data interfaces
CPU verification with directed C tests
Serves as an independent individual contributor to technical project
Proven capability as a problem solver with an ability to work individually or as part of a team
Evaluates issues and defines solutions
Applies advanced knowledge of a single sub-function OR thorough knowledge of multiple sub-functions
Contributes to the development of technical sales documents such as a Statement of Work
Develops and presents technical white papers

Desirable

· Formal verification apps - x-prop, connectivity,CDC

· Formal FPV

· System-wide cache management, coherent and non-coherent NoC verification

· Understanding of AI application in EDA process

· Power aware verification – UPF and or CPF

· gate-level simulation with SDF

· SoC level verification – HW/SW co-verification, multi-mode simulation

· Understanding of assembly language

· DSP verification, model matching techniques

· HW acceleration – emulation

· Verification infrastructure automation – Perl, Python, Java, Tcl, IP-XACT

· Coverage databases e.g., UCDB

Excellent leadership, communication and negotiation skills and time management skills
Self-organisation and ability to respond to changing priorities quickly
Ability to work under pressure
Organisation and problem-solving skills
Self-motivated
Excellent attention to detail